1. Field of the Invention
The present invention relates to memory control technology, particularly for an information processing system and a memory controller for controlling operation of a plurality of memories.
2. Description of the Related Art
A control signal and a data address signal to be transmitted to a memory from a system large scale integrated circuit (LSI) are often shared by a plurality of memories, so as to decrease the number of pins of a system LSI. In such case, a memory controller of the system LSI accesses the same data address in a plurality of memories in the same clock cycle.
In the case of a synchronous dynamic random access memory (SDRAM), when a data processor of the system LSI issues a request Req(A) to the memory controller using a memory access request signal, the memory controller issues a command Cmd(A) (where A denotes data address hereafter) to the memory using a control and data address signal. The command Cmd(A) specifies a reading or writing operation. In the case of an SDRAM, the request Req(A) and the command Cmd(A) may be used for transmission of a burst length of data for the SDRAM.
In the case of the SDRAM, the command Cmd(A) may include a plurality of commands, such as a precharge command, an activate command, a write command, and a read command. Note that each single command Cmd(A) can include at most only one of each of the commands. Either the write command or the read command is always included in the command Cmd(A).
For example, if the command Cmd(A) is transmitted from the memory controller to memory 0 and memory 1, data D0(A) is then transferred between the memory 0 and the memory controller via a memory 0 data signal in response to the command Cmd(A). In addition, data D1(A) is transferred between the memory 1 and the memory controller via a memory 1 data signal. In such case, the data D0(A) and the data D1(A) are transferred in the same clock cycle. In addition, the data D0(A) and the data D1(A) are transferred between the data processor and the memory controller using a request data signal in the same clock cycle.
Accordingly, even if the data processor requests only the data D0 (A) stored in the memory 0, the data D1 (A) of the data address A is also read from the memory 1. In other words, reading unnecessary data D1(A) increases the necessary number of access clock cycles in response to a request from the data processor.
To solve the aforementioned problems, there is a method of specifying a data address in each memory by connecting address lines to each of the memories so as to prevent unnecessary data from being read. However, such connection of a plurality of address lines increases the number of pins of the system LSI.